\doxysubsubsection{RCCEx Exported Constants }
\hypertarget{group___r_c_c_ex___exported___constants}{}\label{group___r_c_c_ex___exported___constants}\index{RCCEx Exported Constants@{RCCEx Exported Constants}}
\doxysubsubsubsubsection*{Topics}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{group___r_c_c_ex___periph___clock___selection}{RCCEx Periph Clock Selection}}
\item 
\mbox{\hyperlink{group___r_c_c___p_l_l2___clock___output}{RCC PLL2 Clock Output}}
\item 
\mbox{\hyperlink{group___r_c_c___p_l_l3___clock___output}{RCC PLL3 Clock Output}}
\item 
\mbox{\hyperlink{group___r_c_c___p_l_l2___v_c_i___range}{RCC PLL2 VCI Range}}
\item 
\mbox{\hyperlink{group___r_c_c___p_l_l2___v_c_o___range}{RCC PLL2 VCO Range}}
\item 
\mbox{\hyperlink{group___r_c_c___p_l_l3___v_c_i___range}{RCC PLL3 VCI Range}}
\item 
\mbox{\hyperlink{group___r_c_c___p_l_l3___v_c_o___range}{RCC PLL3 VCO Range}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_s_a_r_t16___clock___source}{RCCEx USART1/6 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_s_a_r_t1___clock___source}{RCCEx USART1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_s_a_r_t6___clock___source}{RCCEx USART6 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_s_a_r_t234578___clock___source}{RCCEx USART2/3/4/5/7/8 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_s_a_r_t2___clock___source}{RCCEx USART2 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_s_a_r_t3___clock___source}{RCCEx USART3 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_a_r_t4___clock___source}{RCCEx UART4 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_a_r_t5___clock___source}{RCCEx UART5 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_a_r_t7___clock___source}{RCCEx UART7 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_a_r_t8___clock___source}{RCCEx UART8 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___l_p_u_a_r_t1___clock___source}{RCCEx LPUART1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___i2_c1235___clock___source}{RCCEx I2\+C1/2/3/5 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___i2_c1___clock___source}{RCCEx I2\+C1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___i2_c2___clock___source}{RCCEx I2\+C2 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___i2_c3___clock___source}{RCCEx I2\+C3 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___i2_c4___clock___source}{RCCEx I2\+C4 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___r_n_g___clock___source}{RCCEx RNG Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___u_s_b___clock___source}{RCCEx USB Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_a_i1___clock___source}{SAI1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i123___clock___source}{SPI1/2/3 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i1___clock___source}{SPI1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i2___clock___source}{SPI2 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i3___clock___source}{SPI3 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i45___clock___source}{SPI4/5 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i4___clock___source}{SPI4 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i5___clock___source}{SPI5 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_i6___clock___source}{SPI6 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___l_p_t_i_m1___clock___source}{RCCEx LPTIM1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___l_p_t_i_m2___clock___source}{RCCEx LPTIM2 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___l_p_t_i_m345___clock___source}{RCCEx LPTIM3/4/5 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___l_p_t_i_m3___clock___source}{RCCEx LPTIM3 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___f_m_c___clock___source}{RCCEx FMC Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_d_m_m_c___clock___source}{RCCEx SDMMC Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___a_d_c___clock___source}{RCCEx ADC Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_w_p_m_i1___clock___source}{RCCEx SWPMI1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___d_f_s_d_m1___clock___source}{RCCEx DFSDM1 Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___s_p_d_i_f_r_x___clock___source}{RCCEx SPDIFRX Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_e_c___clock___source}{RCCEx CEC Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_l_k_p___clock___source}{RCCEx CLKP Clock Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___t_i_m___prescaler___selection}{RCCEx TIM Prescaler Selection}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___r_c_c___w_w_d_gx}{RCCEx RCC WWDGx}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s}{RCC LSE CSS external interrupt line}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___status}{RCCEx CRS Status}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_source}{RCCEx CRS Synchro\+Source}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider}{RCCEx CRS Synchro\+Divider}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_polarity}{RCCEx CRS Synchro\+Polarity}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___reload_value_default}{RCCEx CRS Reload\+Value\+Default}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___error_limit_default}{RCCEx CRS Error\+Limit\+Default}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___h_s_i48_calibration_default}{RCCEx CRS HSI48\+Calibration\+Default}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___freq_error_direction}{RCCEx CRS Freq\+Error\+Direction}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___interrupt___sources}{RCCEx CRS Interrupt Sources}}
\item 
\mbox{\hyperlink{group___r_c_c_ex___c_r_s___flags}{RCCEx CRS Flags}}
\end{DoxyCompactItemize}


\doxysubsubsubsection{Detailed Description}
\input{group___r_c_c_ex___periph___clock___selection}
\input{group___r_c_c___p_l_l2___clock___output}
\input{group___r_c_c___p_l_l3___clock___output}
\input{group___r_c_c___p_l_l2___v_c_i___range}
\input{group___r_c_c___p_l_l2___v_c_o___range}
\input{group___r_c_c___p_l_l3___v_c_i___range}
\input{group___r_c_c___p_l_l3___v_c_o___range}
\input{group___r_c_c_ex___u_s_a_r_t16___clock___source}
\input{group___r_c_c_ex___u_s_a_r_t1___clock___source}
\input{group___r_c_c_ex___u_s_a_r_t6___clock___source}
\input{group___r_c_c_ex___u_s_a_r_t234578___clock___source}
\input{group___r_c_c_ex___u_s_a_r_t2___clock___source}
\input{group___r_c_c_ex___u_s_a_r_t3___clock___source}
\input{group___r_c_c_ex___u_a_r_t4___clock___source}
\input{group___r_c_c_ex___u_a_r_t5___clock___source}
\input{group___r_c_c_ex___u_a_r_t7___clock___source}
\input{group___r_c_c_ex___u_a_r_t8___clock___source}
\input{group___r_c_c_ex___l_p_u_a_r_t1___clock___source}
\input{group___r_c_c_ex___i2_c1235___clock___source}
\input{group___r_c_c_ex___i2_c1___clock___source}
\input{group___r_c_c_ex___i2_c2___clock___source}
\input{group___r_c_c_ex___i2_c3___clock___source}
\input{group___r_c_c_ex___i2_c4___clock___source}
\input{group___r_c_c_ex___r_n_g___clock___source}
\input{group___r_c_c_ex___u_s_b___clock___source}
\input{group___r_c_c_ex___s_a_i1___clock___source}
\input{group___r_c_c_ex___s_p_i123___clock___source}
\input{group___r_c_c_ex___s_p_i1___clock___source}
\input{group___r_c_c_ex___s_p_i2___clock___source}
\input{group___r_c_c_ex___s_p_i3___clock___source}
\input{group___r_c_c_ex___s_p_i45___clock___source}
\input{group___r_c_c_ex___s_p_i4___clock___source}
\input{group___r_c_c_ex___s_p_i5___clock___source}
\input{group___r_c_c_ex___s_p_i6___clock___source}
\input{group___r_c_c_ex___l_p_t_i_m1___clock___source}
\input{group___r_c_c_ex___l_p_t_i_m2___clock___source}
\input{group___r_c_c_ex___l_p_t_i_m345___clock___source}
\input{group___r_c_c_ex___l_p_t_i_m3___clock___source}
\input{group___r_c_c_ex___f_m_c___clock___source}
\input{group___r_c_c_ex___s_d_m_m_c___clock___source}
\input{group___r_c_c_ex___a_d_c___clock___source}
\input{group___r_c_c_ex___s_w_p_m_i1___clock___source}
\input{group___r_c_c_ex___d_f_s_d_m1___clock___source}
\input{group___r_c_c_ex___s_p_d_i_f_r_x___clock___source}
\input{group___r_c_c_ex___c_e_c___clock___source}
\input{group___r_c_c_ex___c_l_k_p___clock___source}
\input{group___r_c_c_ex___t_i_m___prescaler___selection}
\input{group___r_c_c_ex___r_c_c___w_w_d_gx}
\input{group___r_c_c_ex___e_x_t_i___l_i_n_e___l_s_e_c_s_s}
\input{group___r_c_c_ex___c_r_s___status}
\input{group___r_c_c_ex___c_r_s___synchro_source}
\input{group___r_c_c_ex___c_r_s___synchro_divider}
\input{group___r_c_c_ex___c_r_s___synchro_polarity}
\input{group___r_c_c_ex___c_r_s___reload_value_default}
\input{group___r_c_c_ex___c_r_s___error_limit_default}
\input{group___r_c_c_ex___c_r_s___h_s_i48_calibration_default}
\input{group___r_c_c_ex___c_r_s___freq_error_direction}
\input{group___r_c_c_ex___c_r_s___interrupt___sources}
\input{group___r_c_c_ex___c_r_s___flags}
